The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2008
Filed:
Jan. 11, 2003
Dieter Haupt, Springe, DE;
Klaus Gaedke, Hannover, DE;
Siegfried Schweidler, Gehrden, DE;
Thomson Licensing, Boulogne-Billancourt, FR;
Abstract
The invention deals with a physical layer circuit for the IEEE1394 bus. Considered is a scenario where two clusters of 1394 devices are linked to each other by means of a wireless bridge. The devices of one cluster shall communicate with devices of the other cluster without being bridge aware. Under this scenario there are two different types of 1394 devices existing in each cluster. One device is a bridge portal and will have the bridge functionality. All the other 1394 devices in the cluster will not have the bridge functionality. As the device having the bridge functionality needs to have a specific buffer memory for buffering node-ID packets, usually there are two different types of physical layer circuits required for the different types of 1394 devices. The invention deals with the problem of how it can be realized to use in both different types of 1394 devices the same type of physical layer circuit. The invention solves the problem by means of configuration means in the physical layer circuit. These configuration means enable either to configure the physical layer circuit as a bridge portal physical layer circuit supporting the bridge functionality by buffering said node-ID packets in said buffer memory or else configuring the physical layer circuit as a standard physical layer circuit that disables the buffering of said node-ID packets. The new type of physical layer circuit is pin compatible with a standard physical layer circuit.