The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2008

Filed:

Apr. 19, 2007
Applicants:

Tatsuro Imamura, Tokyo, JP;

Yuji Yamaguchi, Tokyo, JP;

Kazuhiro Shinozaki, Tokyo, JP;

Satoshi Shibazaki, Tokyo, JP;

Yoshitaka Fukuoka, Tokyo, JP;

Hiroyuki Hirai, Fuchu, JP;

Osamu Shimada, Fuchu, JP;

Kenji Sasaoka, Fuchu, JP;

Kenichi Matsumura, Fuchu, JP;

Inventors:

Tatsuro Imamura, Tokyo, JP;

Yuji Yamaguchi, Tokyo, JP;

Kazuhiro Shinozaki, Tokyo, JP;

Satoshi Shibazaki, Tokyo, JP;

Yoshitaka Fukuoka, Tokyo, JP;

Hiroyuki Hirai, Fuchu, JP;

Osamu Shimada, Fuchu, JP;

Kenji Sasaoka, Fuchu, JP;

Kenichi Matsumura, Fuchu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a component built-in wiring board and a manufacturing method thereof capable of further improving component mounting density without deteriorating reliability. The component built-in wiring board includes: a conductive layer () extending in a thickness direction of the board and buried in the board without being exposed from an upper and a lower surface of the board; an electrical/electronic component () having a terminal and buried in the board with the terminal facing the buried conductive layer; a connecting member () provided in a gap between the terminal of the buried electrical/electronic component and the conductive layer to electrically/mechanically connect the terminal and the conductive layer; and two upper and lower insulating layers () which cover an outer surface of the buried electrical/electronic component excluding a portion connected to the connecting member and which are in close contact with a top and a bottom in the board thickness direction of the electrical/electronic component.


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