The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2008
Filed:
Feb. 10, 2005
Reza Tayrani, Marina Del Rey, CA (US);
Jonathan D. Gordon, Hermosa Beach, CA (US);
Reza Tayrani, Marina Del Rey, CA (US);
Jonathan D. Gordon, Hermosa Beach, CA (US);
Raytheon Company, Waltham, MA (US);
Abstract
A Class-E load circuit topology suitable for switching mode Power Amplifiers (PAs). The inventive load includes a shunt inductive element coupled to an output of said amplifier; a series inductive element coupled to said output of said amplifier; and a series capacitive element coupled to said series inductive element. In the illustrative embodiment, the inventive load is operable at frequencies in the range of 8-10 GHz and the shunt inductive element is an inductive bias line for said amplifier. The invention enables an advantageous Class-E amplifier design comprising an input matching network; an active device coupled to the input matching network and a load coupled to the active device and implemented in accordance with the present teachings. Also disclosed is a method for designing a load for use with a Class-E amplifier including the steps of: providing a lumped equivalent circuit representation of the load; optimizing the lumped equivalent circuit representation of the load to achieve near ideal current and voltage operational characteristics over a predetermined frequency range using a time domain simulation; transforming the optimized lumped equivalent circuit representation of the load to a distributed circuit representation; and optimizing the distributed circuit representation of the load to achieve near ideal current and voltage operational characteristics over a predetermined frequency range using a time domain simulation.