The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2008

Filed:

Jul. 20, 2006
Applicant:

Akio Hirata, Kyoto, JP;

Inventor:

Akio Hirata, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
Abstract

A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that is shorter than the clock cycle, wherein only three N-type transistors are connected in series in the input section employing a dynamic circuit. A data signal is input directly to one of the three N-type transistors. On the other hand, a test input signal is input to an AND/OR inverter circuit. The AND/OR inverter circuit receives, as a control signal, the potential of the node obtained as the clock signal passes through two inverter circuits. Therefore, there is required only a short hold time for the test input signal.


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