The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2008
Filed:
Feb. 16, 2006
Perry H. Pelley, Iii, Austin, TX (US);
Troy L. Cooper, Austin, TX (US);
Michael A. Mendicino, Austin, TX (US);
Perry H. Pelley, III, Austin, TX (US);
Troy L. Cooper, Austin, TX (US);
Michael A. Mendicino, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor topography () is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line () arranged within an insulating layer () of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line () within an insulating layer () arranged above a wafer substrate () and forming a silicon layer () upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate () upon an SOI substrate having a conductive line () embedded therein and implanting dopants within the semiconductor topography to form source and drain regions () within an upper semiconductor layer () of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.