The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2008

Filed:

Aug. 12, 2004
Applicants:

Cameron D. Patterson, Blacksburg, VA (US);

Prasanna Sundararajan, Mountain View, CA (US);

Brandon J. Blodget, Santa Clara, CA (US);

Scott P. Mcmillan, Santa Clara, CA (US);

Inventors:

Cameron D. Patterson, Blacksburg, VA (US);

Prasanna Sundararajan, Mountain View, CA (US);

Brandon J. Blodget, Santa Clara, CA (US);

Scott P. McMillan, Santa Clara, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.


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