Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions

Abstract

Instructions of a program are stored in compressed form in a program memory (). In a processor which executes the instructions, a program counter () identifies a position in the program memory. An instruction cache () has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit () includes a decompression section () and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer () identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit () fetches an instruction to be executed from the position identified by the cache pointer. When a cache miss occurs because the instruction to be fetched is not present in the instruction cache, the cache loading unit performs such a cache loading operation. An updating unit () updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that the position identified by the said program counter is maintained consistently at the position in the program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.