Automatic clock based power-down circuit

Abstract

An apparatus and method for automatically transitioning the operation of an electronic device to a reduced power consumption state if an input reference clock signal is stopped or no longer synchronized (locked) with the operation of the electronic device. The electronic device is automatically returned to a normal operating/power consumption state if the reference clock is restarted. Mixed analog and digital electronic components are employed to handle the transition of the electronic device between reduced and normal power consumption states. These components can include a phase frequency detector and a lost_lock detection circuit. The lost_lock detection circuit is typically connected to the output of phase frequency detector and outputs a lost_lock signal if the reference clock signal has stopped or lost_lock with a feedback clock signal. The lost_lock detection circuit operates on at least one error signal outputted by the phase frequency detector and is relatively insensitive to variations in the duty cycle of the reference and feedback clock signals.