Split-gate power module for suppressing oscillation therein

Abstract

The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The dies are mounted on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate. A source of each die is electrically connected to a second area of the conductive layer on the substrate. A gate of each die is electrically connected to a third, common interior central area of the conductive layer on the substrate via separate electrical leads. The leads are sized to substantially the same electrical length and providing a first impedance corresponding to said electrical length from the common area to each gate that will pass the first frequency substantially unattenuated and providing a second impedance from the gate of one die to the gate of a second die that will substantially attenuate the second frequency. In a first embodiment, the leads take the form of one or more jumper wires in series with a film resistor. In a second embodiment, the leads take the form of one or more meandering striplines having predefined impedance characteristics, and one or more gate bonding pads connected to their respective gates with long jumper wires.