The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2008
Filed:
May. 27, 2005
Steven Emerson, Chanhassen, MN (US);
Jonathan Byrn, Kasson, MN (US);
Donald Gabrielson, Rochester, MN (US);
Gary Lippert, Kasson, MN (US);
Steven Emerson, Chanhassen, MN (US);
Jonathan Byrn, Kasson, MN (US);
Donald Gabrielson, Rochester, MN (US);
Gary Lippert, Kasson, MN (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.