The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2008

Filed:

Aug. 17, 2004
Applicants:

John C. Desko, Jr., Wescosville, PA (US);

Bailey R. Jones, Mohnton, PA (US);

Sean Lian, Allentown, PA (US);

Simon John Molloy, Allentown, PA (US);

Vivian Ryan, Hampton, NJ (US);

Inventors:

John C. Desko, Jr., Wescosville, PA (US);

Bailey R. Jones, Mohnton, PA (US);

Sean Lian, Allentown, PA (US);

Simon John Molloy, Allentown, PA (US);

Vivian Ryan, Hampton, NJ (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/283 (2006.01);
U.S. Cl.
CPC ...
Abstract

Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.


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