The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2008

Filed:

May. 26, 2005
Applicants:

Vasile Romega Thompson, Tempe, AZ (US);

Jason Fender, Chandler, AZ (US);

Terry K. Daly, Gilbert, AZ (US);

Jin-wook Jang, Chandler, AZ (US);

Inventors:

Vasile Romega Thompson, Tempe, AZ (US);

Jason Fender, Chandler, AZ (US);

Terry K. Daly, Gilbert, AZ (US);

Jin-Wook Jang, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

Semiconductor packages () that prevent the leaching of gold from back metal layers () into the solder () and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack () including metal pads () and a substrate (). An adhesion/plating layer () is formed on the substrate (). A layer of gold () is plated on the adhesion/plating layer (). The layer of gold is etched in a street area () to expose edge portions () of the layer of gold () and the adhesion/plating layer (). A layer of barrier metal () is deposited to form an edge seal () about the exposed edge portions (). The edge seal () prevents the leaching of gold from back metal layers () into the solder () when the wafer stack () is soldered to a leadframe ().


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