The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2008
Filed:
Nov. 04, 2002
Toshiyuki Nagata, Ibaraki, JP;
Toshiyuki Nagata, Ibaraki, JP;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gatesare formed. These gatesare classed into three groups; namely, first conductivity type peripheral gates, second conductivity type peripheral gates, and array gates. The array gatesand the first conductivity type peripheral gatesare masked such that the second conductivity type peripheral gatesremain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates, while simultaneously doping a first and a second source/drain regionadjacent each of the second conductivity type peripheral gates. The second conductivity type peripheral gatesare then masked such that the first conductivity type peripheral gatesremain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates, while simultaneously doping a first and a second source/drain regionadjacent each of the first conductivity type peripheral gates