The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2008

Filed:

May. 10, 2005
Applicants:

Tobias J. Becker, Bergisch Gladbach, DE;

Adam P. Donlin, Los Gatos, CA (US);

Brandon J. Blodget, Santa Clara, CA (US);

Inventors:

Tobias J. Becker, Bergisch Gladbach, DE;

Adam P. Donlin, Los Gatos, CA (US);

Brandon J. Blodget, Santa Clara, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmably configurable logic-based macro is described. Portions of configuration logic blocks for interconnectivity are assigned. The portions are configured as respective shift registers. Interconnects are routed between design static locations associated to provide interconnectivity between the portions. The portions assigned and routed are saved as a macro file. Inputs and outputs of the macro file are defined in a hardware description language. The hardware description language definition of the inputs and the outputs of the macro file are synthesized to provide a bitstream for programming programmably configurable logic associated with the portions. A shift register-to-shift register module interface boundary is created within an array of the programmably configurable logic.


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