Bus system and information processing system including bus system

Abstract

In a bus connection circuit for connecting buses having different bit widths, number of clock cycles can be reduced, and hardware amount can be reduced. The bus connection circuit connects buses of mutually different bit widths having control lines and data lines connected to a bus master unit and bus slave unit. The control command lines of the buses are connected to a common control command bus to control command information on the buses. The data lines of the buses are connected via a data conversion unit to perform bit width conversion between the buses. An arbitration circuit is provided to perform arbitration of bus right for the buses in response arbitration request. Upon transfer of data between the buses, by obtaining of bus right by sender side bus, write access and rear access between buses is performed.