Semiconductor memory device with reduced multi-row address testing

Abstract

A semiconductor memory device and multi-row address test method reduce the time it takes to perform the multi-row address test. The semiconductor memory device comprises normal memory cell blocks, which can include normal memory cells and spare cells that replace defective cells. The device also includes a redundancy signal generator to output a redundancy signal indicating whether any memory cell blocks include defective cells and address signals of repair word lines corresponding to the defective cells. A redundancy signal decoder decodes the redundancy signal and the address signals of the repair word lines and outputs word line enable signals, and word line drivers that do not enable the repair word lines, but selectively enable the normal word lines in response to the word line enable signals.