The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7336500 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 26, 2008

Filed:

Sep. 03, 2004
Applicants:

Marcus Negron, Santa Cruz, CA (US);

Michael Phipps, Aptos, CA (US);

Inventors:

Marcus Negron, Santa Cruz, CA (US);

Michael Phipps, Aptos, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A demonstration tool for a programmable logic device is provided. The demonstration tool includes a circuit board partially disposed within a transparent block. A collar having an opening defined therein is disposed between the transparent clock and a base of the demonstration tool. The base is designed to enable access to a bottom portion of the circuit board that extends outside of the transparent block and the collar. The bottom portion of the circuit board includes connection ports to power and configure the programmable logic device. A method for embedding a printed circuit board into a housing is also provided.


Find Patent Forward Citations

Negron, Marcus. (2008). Method and apparatus for encapsulating a printed circuit board (U.S. Patent No. 7336500). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7336500

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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