The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2008
Filed:
Mar. 24, 2005
Koichi Matsuo, Tokyo, JP;
Tsutomu Tamaki, Tokyo, JP;
Takuya Suzuki, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A multilayer dielectric substrate includes a first signal via, a second signal via, an internal-layer signal line, an internal-layer ground conductor, and ground vias. The first signal via is connected to a bias-and-control-signal terminal of a high-frequency semiconductor, and is arranged within a region corresponding to the electromagnetic shielding members. The second signal via is arranged outside the region, and is connected to an external terminal for a bias and control signal. The internal-layer signal line connects between the first and the second signal vias. The internal-layer ground conductor is arranged around the first and the second signal vias and the internal-layer signal line. The ground vias are arranged around the first and the second signal vias and the internal-layer signal line, on the internal-layer ground conductor. A resistance film is provided on at least one of an upper surface and a lower surface of the internal-layer signal line.