The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2008

Filed:

Jan. 31, 2006
Applicants:

Akio Hirata, Kyoto, JP;

Takahiro Ichinomiya, Katano, JP;

Takashi Ando, Kusatsu, JP;

Inventors:

Akio Hirata, Kyoto, JP;

Takahiro Ichinomiya, Katano, JP;

Takashi Ando, Kusatsu, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.


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