The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2008
Filed:
Aug. 21, 2006
Applicants:
I-teh Sha, Cupertino, CA (US);
Lifeng Zhang, Shanghai, CN;
Haitao Sun, Shanghai, CN;
Jingrong LI, Shanghai, CN;
Inventors:
I-Teh Sha, Cupertino, CA (US);
LiFeng Zhang, Shanghai, CN;
HaiTao Sun, Shanghai, CN;
JingRong Li, Shanghai, CN;
Assignee:
Huaya Microelectronics, Ltd., , KY;
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract
A delay-locked loop (DLL) to produce a plurality of delayed clock signals comprising combinational logic for false lock detection is provided. The combinational logic uses only a subset of the plurality of delayed clock signals to provide a forward indicator indicating a delay period (Δt) is longer than a desired delay period. The combinational logic further provides a back indicator indicating the delay period (Δt) is shorter than a desired delay period.