The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2008

Filed:

Dec. 16, 2004
Applicants:

Dae Woo Lee, Daejeon, KR;

Tae Moon Roh, Daejeon, KR;

Sung Ku Kwon, Daejeon, KR;

IL Yong Park, Daejeon, KR;

Yil Suk Yang, Daejeon, KR;

Byoung Gon Yu, Daejeon, KR;

Jong Dae Kim, Daejeon, KR;

Inventors:

Dae Woo Lee, Daejeon, KR;

Tae Moon Roh, Daejeon, KR;

Sung Ku Kwon, Daejeon, KR;

Il Yong Park, Daejeon, KR;

Yil Suk Yang, Daejeon, KR;

Byoung Gon Yu, Daejeon, KR;

Jong Dae Kim, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.


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