The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2008

Filed:

Jan. 11, 2005
Applicants:

Bong-seok Suh, Suwon-si, KR;

Ki-chul Park, Suwon-si, KR;

Seung-man Choi, Hwaseong-si, KR;

Il-ryong Kim, Suwon-si, KR;

Inventors:

Bong-Seok Suh, Suwon-si, KR;

Ki-Chul Park, Suwon-si, KR;

Seung-Man Choi, Hwaseong-si, KR;

Il-Ryong Kim, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.


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