The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2008

Filed:

May. 31, 2005
Applicants:

Herbert Johannes Preuthen, Dorfen, DE;

Johann Leyrer, Munich, DE;

Hermann Sauter, Munich, DE;

Inventors:

Herbert Johannes Preuthen, Dorfen, DE;

Johann Leyrer, Munich, DE;

Hermann Sauter, Munich, DE;

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The two or more local tie up cells may be configured to provide electrostatic discharge (ESD) protection to one or more first standard cells. Each of the local tie up cells may be coupled to (i) the one or more first standard cells and (ii) each of the gate voltage signals. The two or more local tie down cells may be configured to provide ESD protection to one or more second standard cells. Each of the local tie down cells may be coupled to (i) the one or more second standard cells and (ii) each of the supply voltage signals.


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