Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit

Abstract

A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one of the internal test signal. The semiconductor integrated circuit further includes a current generator coupled to the delay time measurement terminal, and still further includes a plurality of delay time measurement transistors coupled to the delay time measurement terminal. The delay time measurement transistors have a plurality of control electrodes coupled to the logic circuit to receive the internal test signals. Alternatively, the semiconductor integrated circuit may include an input switching circuit coupled between the logic circuit and the CUT and a pseudo test terminal coupled to the CUT and the logic circuit.