The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2008
Filed:
Jul. 01, 2005
Hugh Sungki O, Fremont, CA (US);
Chih-ching Shih, Pleasanton, CA (US);
Cheng-hsiung Huang, Cupertino, CA (US);
Yow-juang Bill Liu, San Jose, CA (US);
Hugh Sungki O, Fremont, CA (US);
Chih-Ching Shih, Pleasanton, CA (US);
Cheng-Hsiung Huang, Cupertino, CA (US);
Yow-Juang Bill Liu, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.