The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2008

Filed:

Sep. 22, 2005
Applicants:

Niv Amit, Givat Shmuel, IL;

Ronit Bustin, Ra'anana, IL;

Lidor Goren, Netanya, IL;

Omer Heymann, Tel Aviv-Jaffa, IL;

Moshe Leibowitz, Haifa, IL;

Gil Noy, Ramat Gan, IL;

Alex Raphayevich, Kiryat Ekron, IL;

Maya Speiser, Tel Aviv-Jaffa, IL;

Inventors:

Niv Amit, Givat Shmuel, IL;

Ronit Bustin, Ra'anana, IL;

Lidor Goren, Netanya, IL;

Omer Heymann, Tel Aviv-Jaffa, IL;

Moshe Leibowitz, Haifa, IL;

Gil Noy, Ramat Gan, IL;

Alex Raphayevich, Kiryat Ekron, IL;

Maya Speiser, Tel Aviv-Jaffa, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.


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