The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2008
Filed:
Jul. 29, 2004
Patrick R. Bashford, Fort Collins, CO (US);
Brian A. Day, Colorado Springs, CO (US);
Vetrivel Ayyavu, Norcros, GA (US);
Ganesan Viswanathan, Duluth, GA (US);
Patrick R. Bashford, Fort Collins, CO (US);
Brian A. Day, Colorado Springs, CO (US);
Vetrivel Ayyavu, Norcros, GA (US);
Ganesan Viswanathan, Duluth, GA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA interface that utilizes a combination of IOP control and specialized hardware control. The method may include steps as follows. It is determined, preferably based on a value of the Automate bit in a Task File Ram of a Serial ATA interface, whether a Serial ATA device of the Serial ATA interface is being controlled via the IOP or controlled by the specialized Serial ATA automation hardware. When the Serial ATA device is controlled via the IOP, the IOP may decide when to power up/down the Serial ATA interface. When the Serial ATA device is controlled by the specialized Serial ATA automation hardware, the method may proceed as follows. An idle or active condition of a Serial ATA interface utilizing a combination of IOP control and specialized hardware control is then automatically detected. When Serial ATA is in an idle condition, idle time of Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.