The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2008
Filed:
Jan. 21, 2005
Ting Yun Kao, Cupertino, CA (US);
Robert Yin, Castro Valley, CA (US);
Hamish T. Fallside, Los Gatos, CA (US);
Richard P. Burnley, Mountain View, CA (US);
Nicholas Mckay, Edinburgh, GB;
Martin B. Rhodes, Edinburgh, GB;
Stuart A. Nisbet, Edinburgh, GB;
Gareth D. Edwards, Edinburgh, GB;
Allan W. Fyfe, Edinburgh, GB;
Ting Yun Kao, Cupertino, CA (US);
Robert Yin, Castro Valley, CA (US);
Hamish T. Fallside, Los Gatos, CA (US);
Richard P. Burnley, Mountain View, CA (US);
Nicholas McKay, Edinburgh, GB;
Martin B. Rhodes, Edinburgh, GB;
Stuart A. Nisbet, Edinburgh, GB;
Gareth D. Edwards, Edinburgh, GB;
Allan W. Fyfe, Edinburgh, GB;
Xilinx, Inc., San Jose, CA (US);
Abstract
An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.