The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2008

Filed:

Sep. 20, 2005
Applicants:

Kenji Motomochi, Suita, JP;

Marefusa Kurumada, Mukou, JP;

Inventors:

Kenji Motomochi, Suita, JP;

Marefusa Kurumada, Mukou, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device is provided which has a unit by which a fail bit map can be checked instantaneously over the entire address space. The semiconductor memory device is provided with a data logic forcefully controlling circuitwhich forcefully controls the logic of write data into memory cells selected by using a specified address signal or of read data, a specified row forcefully controlling circuitwhich forcefully makes the control of memory cells selected according to specified row addresses the control exercised during operation different from normal operation, or a specified column forcefully controlling circuitwhich forcefully makes the control of memory cells selected according to specified column addresses the control exercised during operation different from normal operation. This forced fail operation mode is selectable aside from normal operation mode.


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