The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2008

Filed:

Apr. 15, 2005
Applicants:

DO Woo Kim, Kyoungki-do, KR;

Chang Yeol Lee, Seoul, KR;

Myeong Kook Gong, Kyoungki-do, KR;

Inventors:

Do Woo Kim, Kyoungki-do, KR;

Chang Yeol Lee, Seoul, KR;

Myeong Kook Gong, Kyoungki-do, KR;

Assignee:

Hynix Semiconductor Inc., Kyoungki-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 31/113 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a SRAM cell and a method of manufacturing the same. The SRAM cell comprises: a pair of access devices; a pair of pull-up devices; a pair of pull-down devices; and at least one metal plate formed on metal interconnection lines in contact with a substrate, having a dielectric film interposed between the metal plate and the metal interconnection lines, so as to increase a cell capacitance, thereby reducing a soft error rate. Herein, one metal plate may be included in each cell. In this case, the metal plate overlaps with a first one of metal interconnection lines of a node side and a node bar side, while being in contact with a second one of the metal interconnection lines of the node side and the node bar side. Also, two metal plates may be included in each cell. In this case, the metal plates overlap, respectively, with one metal interconnection line of metal interconnection lines of a node side and a node bar side, while being in contact with another metal interconnection line of the node side or the node bar side, respectively. Therefore, capacitance is additionally formed to increase cell capacitance, so that variation of the electric potentials of cell nodes, which is caused by generated electrons, is prevented, and thereby soft error can be efficiently reduced.


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