The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2008
Filed:
Jan. 24, 2005
Ming Yin, Hayward, CA (US);
Toshinari Takayanagi, San Jose, CA (US);
Alan Smith, Santa Clara, CA (US);
Ming Yin, Hayward, CA (US);
Toshinari Takayanagi, San Jose, CA (US);
Alan Smith, Santa Clara, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A method is provided for modeling timing characteristics of a circuit block of an integrated circuit, which includes a main circuit and a timing circuit. The method comprises determining an output pin output delay and determining a timing circuit delay. The output pin output delay is an interval of time from a clock signal reaching a clock reference point (CRP) to an output signal arriving at the output pin. The clock reference point is positioned between the timing circuit and the main circuit. The timing circuit delay is an interval of time from a clock signal arriving at a clock input pin to a clock signal arriving at the CRP. The determination of the timing circuit delay is based on a computer simulation of a netlist of circuit elements in the timing circuit.