The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2008
Filed:
Sep. 27, 2006
Murphy Chen, Shindian, TW;
Perlman HU, Shindian, TW;
Murphy Chen, Shindian, TW;
Perlman Hu, Shindian, TW;
Via Technologies, Inc., , TW;
Abstract
In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock signal. The PLL clock signal of the first frequency is sampled with a second clock signal of a second frequency to generate a first sampled signal, wherein the second frequency is different from the first frequency but has a first correlation with the first frequency so that the first sampled signal toggles at a predetermined frequency when the embedded PLL circuit is in a normal operation condition. The embedded PLL circuit is determined to be in an abnormal operation condition if the first sampled signal does not toggle at said predetermined frequency.