Clock divider with glitch free dynamic divide-by change

Abstract

The circuit of this invention performs clock division with dynamic divide-by value change capability. This circuit provides low area and low latency. The clock divider is conventional except for the logic that handles the dynamic divide-by value change. When the divide-by value is changed by the user, such as through software, the changed value is recorded in a register but does not affect the divider immediately. Once the changed divide-by value is recorded, the divider clock output is allowed to continue till it reaches 'low' and is shut off. Then the recorded value is sent to the divider. The divider then generates a clock signal corresponding to the new divide-by value. The clock gating is then disabled and the clock propagates. This implements glitch free clock switching. This implementation of clock selection or switching provides low area and low latency for switching.