The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2008

Filed:

Sep. 30, 2005
Applicant:

George L. Cebry, Glendale, AZ (US);

Inventor:

George L. Cebry, Glendale, AZ (US);

Assignee:

Honeywell International, Inc., Morristown, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A timing control circuit () generates staggered signals from a pulse width modulated signal () providing lossless switching in a DC to DC power converter (). The DC to DC power converter () comprises two input MOSFET switches () coupled to primary windings () of an isolation transformer () and two output MOSFET switches () coupled to secondary windings () of the isolation transformer. The timing circuit () comprises an input terminal () for receiving a pulse width modulated signal () that switches low at time tand high at time t. A first timing output signal circuit () is responsive to the pulse width modulated signal () and provides a first timing output signal () that switches low at time tand high at time tto control one of the input MOSFET switches (). A second timing output signal circuit () is responsive to the pulse width modulated signal () and provides a second timing output signal () that switches high at time tand low at time tto control the other input MOSFET switch (). A third timing output signal circuit () is responsive to the pulse width modulated signal () and provides a third timing output signal () that switches low at time tand high at time tto control one of the output MOSFET switches (). A fourth timing output signal circuit () is responsive to the pulse width modulated signal () and provides a fourth timing output signal () that switches high at time tand low at time tto control the other of the output MOSFET switches (). The times tthrough toccur in sequence.


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