The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2008
Filed:
Jul. 19, 2005
Hugh Sungki O, Fremont, CA (US);
Chih-ching Shih, Pleasanton, CA (US);
Cheng-hsiung Huang, Cupertino, CA (US);
Yow-juang Bill Liu, San Jose, CA (US);
Hugh Sungki O, Fremont, CA (US);
Chih-Ching Shih, Pleasanton, CA (US);
Cheng-Hsiung Huang, Cupertino, CA (US);
Yow-Juang Bill Liu, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
An integrated circuit is disclosed comprising at least one I/O pull-down device for protecting I/O logic circuits from electrostatic discharge (ESD). The turn-on voltage of the parasitic bipolar transistor in the I/O pull-down device is lowered by forming under a portion of the lightly doped drain (LDD) region of a first conductivity type of a conventional MOS transistor a second region of a second conductivity type. A P-N junction is formed between the second region and the source/drain regions. The turn-on voltage of the parasitic bipolar transistor in the I/O pull-down device can be reduced by at least 3 volts from that of a comparable device that does not practice the invention and can be varied by varying the concentration of the dopant. A method for forming the circuit including a process for recovering the current of the I/O pull-down device and its advantages are also disclosed.