The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2008

Filed:

May. 23, 2005
Applicants:

Marcus Halik, Erlangen, DE;

Hagen Klauk, Erlangen, DE;

Ute Zschieschang, Erlangen, DE;

Günter Schmid, Hemhofen, DE;

Inventors:

Marcus Halik, Erlangen, DE;

Hagen Klauk, Erlangen, DE;

Ute Zschieschang, Erlangen, DE;

Günter Schmid, Hemhofen, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

The gate dielectric layer of a thin film field effect transistor is formed as a multilayer layer system having at least one self assembling molecular monolayer (SAM) and a dielectric polymer layer made of an insulating polymer. With comparatively small layer thicknesses of 10 to 50 nanometers, the multilayer gate dielectric layer ensures low leakage currents and enables failsafe operation of the thin film field effect transistor at low supply voltages of less than 5 volts. The gate dielectric layer is robust toward voltages of up to approximately 20 volts and permits the use of a multiplicity of different materials for realizing an underlying electrode.


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