Hybrid linear wire model approach to tuning transistor widths of circuits with rc interconnect

Abstract

A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent 'de-tuning' that typically occurs when all Rs are shorted, 'wire-adjusts' are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.