The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Feb. 20, 2004
Youseff Abdelilah, Holly Springs, NC (US);
Bartholomew Blaner, Underhill Center, VT (US);
Gordon Taylor Davis, Chapel Hill, NC (US);
Jeffrey Haskell Derby, Chapel Hill, NC (US);
Joseph Franklin Garvey, Cary, NC (US);
Malcolm Scott Ware, Austin, TX (US);
Hua YE, Durham, NC (US);
Youseff Abdelilah, Holly Springs, NC (US);
Bartholomew Blaner, Underhill Center, VT (US);
Gordon Taylor Davis, Chapel Hill, NC (US);
Jeffrey Haskell Derby, Chapel Hill, NC (US);
Joseph Franklin Garvey, Cary, NC (US);
Malcolm Scott Ware, Austin, TX (US);
Hua Ye, Durham, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a 'buffer descriptor block,' to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.