The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Dec. 15, 2005
Roy (Dehai) Kong, Cupertino, CA (US);
Wen-chung Chen, Cupertino, CA (US);
Ping Chen, San Jose, CA (US);
Irene (Chih-yiieh) Cheng, San Jose, CA (US);
Tatsang Mak, Milpitas, CA (US);
Xi Liu, Shanghai, CN;
LI Zhang, ShangHai, CN;
LI Sun, Shanghai, CN;
Chenggang Liu, Shanghai, CN;
Roy (Dehai) Kong, Cupertino, CA (US);
Wen-Chung Chen, Cupertino, CA (US);
Ping Chen, San Jose, CA (US);
Irene (Chih-Yiieh) Cheng, San Jose, CA (US);
Tatsang Mak, Milpitas, CA (US);
Xi Liu, Shanghai, CN;
Li Zhang, ShangHai, CN;
Li Sun, Shanghai, CN;
Chenggang Liu, Shanghai, CN;
Via Technologies, Inc., Hsin-Tien, Taipei, TW;
Abstract
Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.