The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Oct. 29, 2004
Applicants:
Atul K. Jain, Dallas, TX (US);
Venugopal Puvvada, Bangalore, IN;
Jayashree Saxena, Richardson, TX (US);
Inventors:
Atul K. Jain, Dallas, TX (US);
Venugopal Puvvada, Bangalore, IN;
Jayashree Saxena, Richardson, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract
A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one worst-case SDF for all modes. The multiple SDFs account for the impact of dynamic voltage drops on delays in addition to static IR drops.