The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Oct. 29, 2002
Axel K. Kloth, Mountain View, CA (US);
Paul Bergantino, Lexington, MA (US);
Moshe De-leon, Kiron, IL;
Daniel Fu, Saratoga, CA (US);
Stephen M. Mills, Sharon, MA (US);
Jeremy Bicknell, Carlsbad, CA (US);
Warner Andrews, Boulder, CO (US);
Axel K. Kloth, Mountain View, CA (US);
Paul Bergantino, Lexington, MA (US);
Moshe De-Leon, Kiron, IL;
Daniel Fu, Saratoga, CA (US);
Stephen M. Mills, Sharon, MA (US);
Jeremy Bicknell, Carlsbad, CA (US);
Warner Andrews, Boulder, CO (US);
Mindspeed Technologies, Inc., Newport Beach, CA (US);
Abstract
A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.