The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
Jun. 30, 2005
Young Sir Chung, Chandler, AZ (US);
Robert W. Baird, Gilbert, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Gregory W. Grynkewich, Gilbert, AZ (US);
Eric J. Salter, Scottsdale, AZ (US);
Young Sir Chung, Chandler, AZ (US);
Robert W. Baird, Gilbert, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Gregory W. Grynkewich, Gilbert, AZ (US);
Eric J. Salter, Scottsdale, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit device includes a magnetic random access memory ('MRAM') architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.