Dual loop pll, and multiplication clock generator using dual loop pll

Abstract

To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase comparatorfor comparing phases, and a frequency comparison loop having a frequency comparatorfor comparing frequencies, wherein the frequency comparatorcarries out frequency comparison using an input signal inputted from a calibration clock line CLcal, the input signal being different from a reference clock signal inputted from an external reference clock line CLex, the reference clock signal being used for a phase comparator. Moreover, multiplication clock generators are configured using the dual loop PLL.