The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2008

Filed:

Aug. 26, 2005
Applicants:

Eisaku Maeda, Takatsuki, JP;

Hiroshi Ando, Ibaraki, JP;

Jinsaku Kaneda, Suita, JP;

Akihiro Maejima, Takatsuki, JP;

Hiroki Matsunaga, Takatsuki, JP;

Inventors:

Eisaku Maeda, Takatsuki, JP;

Hiroshi Ando, Ibaraki, JP;

Jinsaku Kaneda, Suita, JP;

Akihiro Maejima, Takatsuki, JP;

Hiroki Matsunaga, Takatsuki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal. In this driver circuit, the driving current of the one PMOS transistor is higher than the driving current of the one NMOS transistor.


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