The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2008
Filed:
May. 02, 2005
Sheng Teng Hsu, Camas, WA (US);
Jong-jan Lee, Camas, WA (US);
Jer-shen Maa, Vancouver, WA (US);
Douglas J. Tweet, Camas, WA (US);
Wei-wei Zhuang, Vancouver, WA (US);
Sheng Teng Hsu, Camas, WA (US);
Jong-Jan Lee, Camas, WA (US);
Jer-Shen Maa, Vancouver, WA (US);
Douglas J. Tweet, Camas, WA (US);
Wei-Wei Zhuang, Vancouver, WA (US);
Sharp Laboratories of America, Inc., Camas, WA (US);
Abstract
A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.