Iterative architecture for hierarchical scheduling

Abstract

Conventional schedulers employ designs allocating specific processor and memory resources, such as memory for configuration data, state data, and scheduling engine processor resources for specific aspects of the scheduler, such as layers of the scheduling hierarchy, each of which consumes dedicated processor and memory resources. A generic, iterative scheduling engine, applicable to an arbitrary scheduling hierarchy structure having a variable number of hierarchy layers, receives a scheduling hierarchy structure having a predetermined number of layers, and allocates scheduling resources such as instructions and memory, according to scheduling logic, in response to design constraints and processing considerations. The resulting scheduling logic processes the scheduling hierarchy in iterative manner which allocates the available resources among the layers of the hierarchy, such that the scheduler achieves throughput requirements corresponding to enqueue and dequeue events with consideration to the number of layers in the scheduling hierarchy and the corresponding granularity of queuing.