The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2008

Filed:

Apr. 21, 2004
Applicants:

Katsuyuki Kawamura, Nara, JP;

Yasuyuki Shirasaka, Sakai, JP;

Inventors:

Katsuyuki Kawamura, Nara, JP;

Yasuyuki Shirasaka, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A decoder circuit of the present invention, mounted on an integrated circuit, decodes input voltage Vin supplied to a single external input terminal into three or more control outputs, and an object of the present invention is to reduce the size of a chip. The foregoing decoder circuit includes: a P-type transistor in which an emitter is connected to a power source line of high level, a base is connected to the external input terminal, and a collector is an output terminal of a first control output; and an N-type transistor in which an emitter is connected to a power source line of low level, a base is connected to the external input terminal, and a collector is an output terminal of a second control output, and decodes the control outputs to three or more sets of data by carrying out logic operations. Therefore, as compared to the case of using a comparator requiring many transistors, a constant current source, and other elements, one each transistor is required for each of the two control outputs to be generated. This facilitates size reduction of a chip.


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