Ramp generator and relative row decoder for flash memory device

Abstract

A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp. A respective local ramp generating circuit is provided for each array sector and for the array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.