Compensating capacitive dielectric absorption induced frequency error in a phase locked loop

Abstract

A PLL comprises a VCO and a loop filter, wherein the VCO generates an AC output signal having a frequency which depends on an applied control voltage, and wherein the loop filter provides a control voltage to the VCO. The control voltage reflects determined phase differences between a potentially frequency divided output signal of the VCO and a reference signal. When operating the PLL, frequency deviations between a potentially frequency divided output signal of the VCO and a reference signal are detected and in addition, a resolution employed for detecting the frequency deviations is lower than a resolution employed for determining the phase differences. In case a frequency deviation is detected, a direct-current voltage shift is added to the control voltage provided by the loop filter.