The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2008
Filed:
Nov. 29, 2002
Atsushi Hirabayashi, Tokyo, JP;
Kenji Komori, Kanagawa, JP;
Atsushi Hirabayashi, Tokyo, JP;
Kenji Komori, Kanagawa, JP;
Sony Corporation, , JP;
Abstract
A conventional multiplier which uses a MOS transistor has a subject that, in order to compensate for a variation of a bias voltage or the like, it is necessary to add a complicated correcting circuit to an outputting section or the like, and the circuit scale becomes great and the power consumption increases. A multiplier includes NMOS transistors () and constant voltage sources () connected to the gates of the NMOS transistors (), respectively, and the voltage value of a constant voltage source () and the voltage value of another constant voltage source () are set equal to each other. Further, the NMOS transistor () and the NMOS transistor () are formed same as each other.